We are looking for an ASIC/ FPGA engineer, to Join Ceragon FPGA team in developing next generation backhaul communication systems.
In this role you will be required for:
Aspects of ASIC design activity: Coding, verification support.
All aspects of FPGA design activity: Coding, Synthesizing, verification support and LAB bring up.
Participate in System definitions for current and next generation products.

B.Sc. degree from a leading university. 2-4 years experience in VLSI design, at least 1 of them in FPGA design. Experience in system ramp up and FPGA debug. Excellent system understanding. Deep understanding of SDC. Experience with networking advantage. Experience with UVM verification flow advantage. Experience with board development advantage. Experience with ASIC design advantage. Team player. High motivation to excel